A novel hybrid topology for Network on Chip.

K. Swaminathan Sandeep Gopi Nambiar Rajkumar G. Lakshminarayanan Seok-Bum Ko

Published in: CCECE (2014)

Keyphrases

network on chip
routing algorithm
interconnection networks
network simulator
multi processor
data transfer
packet switched
shortest path
fault tolerant
response time
shared memory
power dissipation