A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device.
Santosh GhoshLuis S. KidaSoham Jayesh DesaiReshma LalPublished in: IACR Cryptol. ePrint Arch. (2020)
Keyphrases
- field programmable gate array
- xilinx virtex
- hardware implementation
- embedded systems
- hardware architecture
- programmable logic
- parallel computing
- software implementation
- hardware design
- image processing algorithms
- computing systems
- digital signal processing
- reconfigurable hardware
- hardware description language
- low power consumption
- fpga device
- fpga implementation
- fpga technology
- low cost
- data acquisition
- hardware software
- dedicated hardware
- main memory
- massively parallel
- real time
- general purpose processors
- hardware software co design
- parallel architecture
- single chip
- control unit
- high end
- computer systems
- high speed
- advanced encryption standard