Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors.
Ahmed AbousamraAlex K. JonesRami G. MelhemPublished in: IEEE Trans. Parallel Distributed Syst. (2012)
Keyphrases
- access latency
- memory access
- prefetching
- network on chip
- shared memory
- cache hit ratio
- multithreading
- response time
- data access
- routing algorithm
- access patterns
- scheduling algorithm
- main memory
- memory management
- caching scheme
- data broadcast
- distributed memory
- web documents
- parallel computing
- data transfer
- hit ratio
- message passing
- high speed
- processing units
- low cost
- single chip
- parallel algorithm
- data management
- mobile clients
- multi channel
- mobile devices
- high volume
- data structure
- hardware implementation