A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.

Jianfeng Zhu Hu He Dong Wu Liyang Pan

Published in: J. Electron. Test. (2011)

Keyphrases

cost efficient
high speed
governmental organizations
low cost
low power
field programmable gate array
real time image processing
real time
hardware implementation
signal processing
fpga implementation
data sets
genetic algorithm
hardware design
single chip