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Highly Efficient Modulo Loop Pipeline For High Level Synthesis.
Chang Wu
Jundong Xie
Kexin Wang
Published in:
ASICON (2021)
Keyphrases
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highly efficient
high level synthesis
parallel architecture
parallel processing
hardware implementation
low cost
shared memory
design space exploration
low latency
low complexity
parallel implementation
case study
data structure
search algorithm
pattern recognition
distributed memory