A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion.
Sultan AlqahtaniYiqun ZhuQizhi ShiXiaolin MengXinhua WangPublished in: FPT (2022)
Keyphrases
- hardware implementation
- matrix inversion
- efficient implementation
- processing elements
- parallel architecture
- signal processing
- pipelined architecture
- field programmable gate array
- monte carlo
- pattern recognition
- computational cost
- image processing algorithms
- hardware design
- parallel implementation
- parallel architectures
- neural network
- image processing
- computer vision