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A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion.
Sultan Alqahtani
Yiqun Zhu
Qizhi Shi
Xiaolin Meng
Xinhua Wang
Published in:
FPT (2022)
Keyphrases
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hardware implementation
matrix inversion
efficient implementation
processing elements
parallel architecture
signal processing
pipelined architecture
field programmable gate array
monte carlo
pattern recognition
computational cost
image processing algorithms
hardware design
parallel implementation
parallel architectures
neural network
image processing
computer vision