Generation of very large circuits to benchmark the partitioning of FPGA.

Joachim Pistorius Edmée Legai Michel Minoux

Published in: ISPD (1999)

Keyphrases

high speed
power reduction
real world
real time image processing
real time
neural network
information retrieval
hardware implementation
comparative analysis
generation process
hardware design
delay insensitive
database
signal processing
circuit design