Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking.
Maher FakihKim GrüttnerMartin FränzleAchim RettbergPublished in: DATE (2013)
Keyphrases
- model checking
- temporal logic
- formal specification
- formal verification
- model checker
- finite state machines
- finite state
- temporal properties
- pspace complete
- partial order reduction
- automated verification
- bounded model checking
- symbolic model checking
- verification method
- reachability analysis
- epistemic logic
- concurrent systems
- process algebra
- timed automata
- transition systems
- modal logic
- computation tree logic
- formal methods
- satisfiability problem
- search algorithm
- coalition logic
- artificial intelligence