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An improved transmission scheme for error-prone inter-chip network-on-chip communication links implemented on FPGAs.

Saif UddinJohnny Öberg
Published in: FPGAworld (2013)
Keyphrases
  • error prone
  • network on chip
  • routing algorithm
  • low cost
  • ad hoc networks
  • power dissipation
  • wireless ad hoc networks
  • image compression
  • wireless networks
  • embedded systems