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FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration.
Afandi Ahmad
Abbes Amira
Paul Raymond Nicholl
Benjamin Krill
Published in:
J. Real Time Image Process. (2013)
Keyphrases
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hardware implementation
hardware architecture
efficient implementation
hardware architectures
neural network
web services
human faces
facial features
parallel processing
parallel implementation
face verification
partial information