Model Checking Timed Automata.
Sergio YovinePublished in: European Educational Forum: School on Embedded Systems (1996)
Keyphrases
- timed automata
- model checking
- temporal logic
- reachability analysis
- model checker
- formal specification
- partial order reduction
- formal verification
- symbolic model checking
- finite state
- finite state machines
- temporal properties
- automated verification
- computation tree logic
- bounded model checking
- epistemic logic
- process algebra
- pspace complete
- verification method
- formal methods
- transition systems
- concurrent systems
- theorem prover
- satisfiability problem
- abstract interpretation
- asynchronous circuits
- real time
- software engineering
- reinforcement learning