FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.
Jason CongChang WuPublished in: DAC (1997)
Keyphrases
- high speed
- logic synthesis
- power reduction
- analog circuits
- low power
- power consumption
- logic circuits
- objective function
- gate array
- fpga device
- real time
- hardware implementation
- parallel processing
- low cost
- program synthesis
- signal processing
- analog vlsi
- shift register
- field programmable gate array
- fine grain
- data acquisition