Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture.
Paul M. HeystersGerard K. RauwerdaGerard J. M. SmitPublished in: IPDPS (2004)
Keyphrases
- hardware implementation
- layered architecture
- fpga technology
- reconfigurable hardware
- architectural design
- dynamic reconfiguration
- hardware architecture
- low cost
- design considerations
- dedicated hardware
- software implementation
- instruction set
- smart camera
- functional units
- parallel architecture
- field programmable gate array
- management system
- vlsi architecture
- memory management
- network architecture
- hardware architectures
- systolic array
- embedded systems
- heterogeneous computing