A proposed FPGA-based parallel architecture for matrix multiplication.
Syed Manzoor QasimShuja Ahmad AbbasiBandar AlmasharyPublished in: APCCAS (2008)
Keyphrases
- parallel architecture
- matrix multiplication
- distributed memory
- hardware implementation
- shared memory
- message passing
- parallel implementation
- hardware architecture
- systolic array
- high level synthesis
- efficient implementation
- parallel processing
- synthetic aperture sonar
- field programmable gate array
- signal processing
- matrix factorization
- data flow
- image processing
- distributed systems
- higher order
- bayesian networks