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A low-power instruction replay mechanism for design of resilient microprocessors.
Rance Rodrigues
Arunachalam Annamalai
Sandip Kundu
Published in:
ACM Trans. Embed. Comput. Syst. (2014)
Keyphrases
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low power
single chip
low cost
power consumption
low power consumption
high speed
logic circuits
gate array
vlsi architecture
high power
real time
digital signal processing
power dissipation
mixed signal
wireless transmission
vlsi circuits
cmos technology
design considerations
parallel processing