FPGA implementations of HEVC sub-pixel interpolation using high-level synthesis.
Firas Abdul GhaniErcan KalaliIlker HamzaogluPublished in: DTIS (2016)
Keyphrases
- high level synthesis
- parallel architecture
- hardware architectures
- hardware implementation
- software implementation
- displacement estimation
- bilinear interpolation
- edge direction
- field programmable gate array
- distributed memory
- general purpose processors
- pixel values
- efficient implementation
- detected edges
- high speed
- low cost
- parallel processing
- interpolation method
- high efficiency video coding
- pixel wise
- shared memory
- video compression
- signal processing
- input image
- partial derivatives
- design space exploration
- multiview video coding
- message passing
- data processing
- bayesian networks
- case study
- image processing