An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.

Jie Shao Ning Ye Xiao-Yan Zhang

Published in: CSSE (4) (2008)

Keyphrases

floating point
floating point arithmetic
fixed point
square root
instruction set
floating point unit
sparse matrices
fast fourier transform
interval arithmetic
parallel processing
field programmable gate array
fine grain
embedded systems
hardware implementation
data flow