A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.
Kesami HagiwaraTomoichi HayashiShumpei KawasakiFumio ArakawaOleg EndoHayato NomuraAkira TsukamotoDuong NguyenBinh NguyenAnh TranHoan HyunhIkuo KudohCong-Kha PhamPublished in: COOL CHIPS (2018)
Keyphrases
- pipelined architecture
- parallel architecture
- management system
- hardware implementation
- fpga device
- reconfigurable hardware
- hardware architecture
- pipeline architecture
- artificial intelligence
- real time
- hardware design
- field programmable gate array
- dedicated hardware
- software implementation
- hardware software co design
- low cost
- expert systems
- level parallelism
- fpga hardware
- hardware and software
- low power
- fpga implementation
- fpga technology
- hardware software
- systolic array
- machine learning
- ubiquitous computing
- high speed
- multithreading
- ai systems
- edge information
- weighted graph
- parallel processing
- subsumption architecture
- cloud computing
- heterogeneous computing
- case based reasoning