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Low-voltage gm-enhanced CMOS differential pairs using positive feedback.

Jaime Ramírez-AnguloBelén CalvoRamón González CarvajalAntonio J. López-Martín
Published in: ISCAS (2010)
Keyphrases
  • low voltage
  • positive feedback
  • cmos technology
  • power line
  • design considerations
  • negative feedback
  • random access memory
  • power management
  • low power
  • learning environment