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Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs.
Zheng Wang
Alessandro Littarru
Emmanuel Ikechukwu Ugwu
Shazia Kanwal
Anupam Chattopadhyay
Published in:
ISVLSI (2016)
Keyphrases
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fault tolerant
fault tolerance
design methodology
design process
distributed systems
embedded systems
safety critical
load balancing
evolvable hardware
artificial intelligence
low cost
directed graph
hardware and software
graph structure