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Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA.
Makoto Saen
Tadanobu Toba
Yusuke Kanno
Published in:
IEICE Trans. Electron. (2017)
Keyphrases
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error tolerant
parallel architecture
high speed
hardware implementation
hardware architecture
graph matching
hardware design
low power
data structure
subgraph isomorphism
cmos technology
fpga device
neural network
social networks
power consumption