Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102].
Chunyu PengYouwu TaoWenjuan LuZhengping LiXinchun JiJinlong YanJunning ChenPublished in: IEICE Electron. Express (2015)