9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS.
Xiang GaoOlivier BurgHaisong WangWanghua WuCao-Thong TuKonstantinos ManetakisFan ZhangLuns TeeMustafa YaylaSining XiangRandy TsangLi LinPublished in: ISSCC (2016)
Keyphrases
- metal oxide semiconductor
- high speed
- circuit design
- power consumption
- low power
- cmos technology
- cmos image sensor
- random sampling
- nm technology
- integrated circuit
- database
- low cost
- silicon on insulator
- mixed signal
- sampling strategy
- single chip
- sampling algorithm
- packet loss
- delay insensitive
- frequency band
- sample size