Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress.
Ruben VazquezAnn Gordon-RossGreg StittPublished in: CODES+ISSS (2019)
Keyphrases
- hardware implementation
- memory hierarchy
- field programmable gate array
- low cost
- single chip
- memory access
- hardware architecture
- real time
- parallel hardware
- embedded processors
- hardware design
- prediction accuracy
- hardware and software
- orders of magnitude
- dedicated hardware
- software implementation
- power reduction
- fpga implementation
- data acquisition
- high speed
- image processing
- computing power
- low power
- efficient implementation
- resource consumption
- memory management
- signal processing
- reconfigurable hardware
- data access
- low power consumption
- hardware description language
- query processing
- xilinx virtex
- programmable logic
- multithreading
- cache misses
- computer systems
- hardware software
- computing systems
- computer architecture
- fpga technology
- hardware software co design