A Hardware Packet Re-Sequencer Unit for Network Processors.
Michael MeitingerRainer OhlendorfThomas WildAndreas HerkersdorfPublished in: ARCS (2008)
Keyphrases
- processing units
- content addressable memory
- real time
- packet size
- parallel computation
- functional units
- intermediate nodes
- bandwidth requirements
- parallel algorithm
- massively parallel
- network traffic
- packet switching
- peer to peer
- low cost
- parallel processing
- high end
- processor core
- embedded processors
- switched networks
- internet protocol
- gigabit ethernet
- packet filtering
- network devices
- transmission rate
- network simulator
- control unit
- parallel architectures
- network design
- hardware implementation
- end to end
- network structure
- wireless sensor networks