A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory.
Xiaowei ChenSeyed Alireza PourbakhshJingyan FuNa GongJinhui WangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2018)
Keyphrases
- power dissipation
- low cost
- power consumption
- random access memory
- memory subsystem
- memory requirements
- chip design
- cmos technology
- high speed
- analog vlsi
- multithreading
- level parallelism
- memory space
- computing power
- memory usage
- low power
- state information
- computational power
- processor core
- neural network
- digital signal processing
- memory access
- functional units
- processing units
- digital signal processors
- phase locked loop