Login / Signup
A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process.
Abhirup Lahiri
Nitin Gupta
Anand Kumar
Pradeep Dhadda
Published in:
IEEE J. Solid State Circuits (2015)
Keyphrases
</>
feedback loop
input data
neural network
search space
development process
control signals
desired output