Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.
Masum HossainAmlan NagWaleed El-HalwagyA. K. M. Delwar Hossain AurangozebPublished in: A-SSCC (2016)
Keyphrases
- low power
- high speed
- vlsi architecture
- low cost
- power consumption
- mixed signal
- cmos technology
- single chip
- nm technology
- digital signal processing
- real time
- power dissipation
- low power consumption
- image sensor
- high power
- vlsi circuits
- logic circuits
- wireless transmission
- signal processor
- circuit design
- design methodology
- vlsi implementation
- np complete
- signal processing
- image processing