Implications of VHDL timing models on simulation and software synthesis.
Venkatram KrishnaswamyRajesh GuptaPrithviraj BanerjeePublished in: J. Syst. Archit. (1997)
Keyphrases
- simulation models
- hardware design
- mathematical models
- data sets
- software tools
- simulation model
- complex systems
- probabilistic model
- model selection
- real time
- machine learning
- multi agent
- analytical model
- social networks
- hardware software
- simulation software
- simulation environment
- autoregressive
- monte carlo simulation
- case study
- user interface
- software systems
- software development
- software engineering