A reconfigurable fault-tolerant systolic signal processor.
Richard R. ShivelyAllen L. GorinPublished in: ICASSP (1989)
Keyphrases
- fault tolerant
- signal processor
- systolic array
- signal processing
- low power
- interconnection networks
- low cost
- fault tolerance
- single chip
- hardware implementation
- distributed systems
- load balancing
- power consumption
- safety critical
- high availability
- parallel architecture
- image processing
- computer vision
- state machine
- image restoration
- peer to peer
- digital images
- fault isolation
- feature extraction