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Real-Time and Low-Memory Multi-Faces Detection System Design With Naive Bayes Classifier Implemented on FPGA.

Kuan-Yu ChouYon-Ping Chen
Published in: IEEE Trans. Circuits Syst. Video Technol. (2020)
Keyphrases
  • low memory
  • fpga device
  • fpga hardware
  • naive bayes classifier
  • naive bayes
  • feature selection
  • computational complexity
  • high dimensional
  • pipelined architecture