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Highly efficient, limited range multipliers for LUT-based FPGA architectures.
Richard H. Turner
Roger F. Woods
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2004)
Keyphrases
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highly efficient
low cost
low latency
low complexity
computer vision
hardware implementation
discriminative learning
multithreading
real time image processing
high speed
sat solvers