Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity.
Michele MastellaFabio TosoGiuseppe SciortinoEnrico PratiGiorgio FerrariPublished in: AICAS (2020)
Keyphrases
- low power
- synaptic weights
- floating gate
- biologically plausible
- power consumption
- high speed
- low cost
- neural network model
- neural network
- artificial neural networks
- biologically inspired
- single chip
- spiking neurons
- input patterns
- cmos technology
- spiking neural networks
- vlsi circuits
- low power consumption
- digital signal processing
- feed forward
- image sensor
- mixed signal
- pso algorithm
- real time
- power reduction
- gate array
- input pattern
- nm technology
- ultra low power
- battery powered
- logic circuits
- power dissipation
- energy efficiency