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Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes.
Peng-Wei Zhang
Sheng Jiang
Francis C. M. Lau
Chiu-Wing Sham
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2022)
Keyphrases
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hardware architecture
decoding algorithm
hardware implementation
error correction
hardware architectures
associative memory
hadamard transform
computer vision
information systems
pattern recognition
processing elements
feature extraction
probabilistic model
software engineering