Radix-4 Max-log-MAP parallel turbo decoder architecture with a new cache memory data flow for LTE.
Trio Adiono MarvinPublished in: ISPACS (2012)
Keyphrases
- data flow
- memory hierarchy
- control flow
- systolic array
- database machine
- data transfer
- multithreading
- memory access
- main memory
- object oriented software
- shared memory
- parallel architecture
- processing elements
- parallel processing
- level parallelism
- memory bandwidth
- memory subsystem
- parallel computing
- digital signal processing
- object oriented
- distributed memory
- processing units
- computer architecture
- quality of service
- turbo codes
- data access
- shared memory multiprocessor
- query processing
- parallel implementation
- cache misses
- memory management
- hardware implementation
- bitstream
- low complexity
- fourth generation
- database management systems