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Pruning Binarized Neural Networks Enables Low-Latency, Low-Power FPGA-Based Handwritten Digit Classification.
Syamantak Payra
Gabriel Loke
Yoel Fink
Joseph D. Steinmeyer
Published in:
HPEC (2023)
Keyphrases
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low power
low latency
handwritten digits
high speed
low cost
power consumption
real time
character recognition
feature vectors
decision trees
supervised learning
handwritten chinese
feature space
classification algorithm
logic circuits
image processing