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Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems.
Akram Ben Ahmed
Michael Conrad Meyer
Yuichi Okuyama
Abderazek Ben Abdallah
Published in:
MCSoC (2014)
Keyphrases
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network on chip
routing algorithm
multi processor
network simulator
packet switched
data transfer
distributed systems
shortest path
single processor
interconnection networks
software implementation
power dissipation
multi core processors