A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS.

Bob Verbruggen Kazuaki Deguchi Badr Malki Jan Craninckx

Published in: VLSIC (2014)

Keyphrases

power consumption
analog to digital converter
circuit design
low power
power supply
low cost
dynamic environments
hd video
high speed
synthetic aperture radar
single chip
metal oxide semiconductor
digital libraries
maximum likelihood
parameter estimation
sar images