Scalable network-on-chip architecture for configurable neural networks.

Dmitri Vainbrand Ran Ginosar

Published in: Microprocess. Microsystems (2011)

Keyphrases

network on chip
neural network
multi processor
network simulator
network architecture
routing algorithm
packet switched
program execution
data transfer
single processor
real time
associative memory
pattern recognition
response time
shared memory
multi core processors