A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing.
Parisa Mashreghi-MoghadamyTarek Ould-BachirzYvon SavariayPublished in: ISCAS (2022)
Keyphrases
- hardware design
- hardware implementation
- hardware architecture
- field programmable gate array
- fpga implementation
- general purpose processors
- digital signal processors
- general purpose
- real time traffic
- low cost
- packet switching
- hardware architectures
- natural language
- efficient implementation
- natural language processing
- management system
- signal processing
- stock market
- high speed
- real time