A Hardware Architecture For Reconfigurable Intelligent Surfaces with Minimal Active Elements for Explicit Channel Estimation.
George C. AlexandropoulosEvangelos VlachosPublished in: ICASSP (2020)
Keyphrases
- hardware architecture
- hardware implementation
- channel estimation
- field programmable gate array
- communication systems
- cdma systems
- multipath
- ofdm system
- fading channels
- estimation algorithm
- efficient implementation
- hardware architectures
- frequency selective
- low cost
- bit error rate
- processing elements
- signal processing
- parallel computing
- embedded systems
- xilinx virtex
- associative memory
- wireless channels
- computational complexity