An ASIC implementation of a low power robust invisible watermarking processor.
P. KarthigaikumarK. BaskaranPublished in: J. Syst. Archit. (2011)
Keyphrases
- low power
- single chip
- high speed
- low cost
- power consumption
- signal processor
- cmos technology
- vlsi architecture
- gate array
- high power
- logic circuits
- ultra low power
- wireless transmission
- vlsi circuits
- efficient implementation
- hardware implementation
- low power consumption
- digital signal processing
- mixed signal
- delay insensitive
- digital images
- instruction set
- computer architecture
- design methodology
- hardware architecture
- watermarking technique
- power reduction
- application specific