Sign in
Design, Simulation, and Implementation of a CMOS Analog Decoder for (480, 240) Low-Density Parity-Check Code.
Zhe Zhao
Kai Yang
Hao Zheng
Fei Gao
Xiangyuan Bu
Published in:
IEEE Access (2017)
Keyphrases
</>
circuit design
vlsi architecture
low density parity check
ldpc codes
low power
analog to digital converter
low complexity
vlsi implementation
decoding algorithm
high speed
error correction
cmos technology
low cost
power consumption