Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.

Feng Gao John P. Hayes

Published in: DAC (2005)

Keyphrases

power reduction
power consumption
low power
cmos technology
power dissipation
high speed
nm technology
low cost
power saving
delay insensitive
analog vlsi
low voltage
energy efficiency
digital signal processing
circuit design
finite state machines
scheduling problem