High-speed and low-power design of parallel turbo decoder.
Zhiyong HeSébastien RoyPaul FortierPublished in: ISCAS (6) (2005)
Keyphrases
- low power
- high speed
- single chip
- low power consumption
- vlsi architecture
- logic circuits
- low cost
- power consumption
- digital signal processing
- gate array
- mixed signal
- cmos technology
- power dissipation
- high power
- vlsi circuits
- power reduction
- wireless transmission
- ultra low power
- design process
- nm technology
- real time
- frame rate
- image processing