Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier.
Xianyang JiangPeng XiaoMeikang QiuGaofeng WangPublished in: Microprocess. Microsystems (2013)
Keyphrases
- floating point
- pipeline architecture
- hardware implementation
- sparse matrices
- square root
- fixed point
- instruction set
- signal processing
- floating point arithmetic
- efficient implementation
- field programmable gate array
- application specific
- interval arithmetic
- computer vision
- graphical models
- pattern recognition
- similarity measure