Improving utilization rate of semi-parallel successive cancellation architecture for polar codes using 2-bit decoding.
Dinesh Kumar DevadossShantha Selva Kumari Rama PackiamPublished in: Turkish J. Electr. Eng. Comput. Sci. (2022)
Keyphrases
- decoding algorithm
- error correcting codes
- master slave
- distributed processing
- parity check
- parallel processing
- error correcting
- decoding complexity
- ldpc codes
- logical operations
- error control
- shared memory
- software architecture
- design considerations
- processing elements
- frequency domain
- parallel architecture
- processing units
- multi processor
- bit parallel
- real time
- level parallelism
- reed solomon
- low density parity check
- multi core processors
- management system
- computer architecture
- parallel computing