Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs.
Matteo Dall'OssoGianluca BiccariLuca GiovanniniDavide BertozziLuca BeniniPublished in: ICCD (2012)
Keyphrases
- multi processor
- network on chip
- program execution
- single processor
- shared memory
- multi core processors
- data transfer
- routing algorithm
- distributed memory
- object oriented
- parallel architectures
- parallel processors
- network simulator
- interconnection networks
- parallel computers
- data flow
- parallel algorithm
- response time