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A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation.
Lianxi Liu
Junchao Mu
Zhangming Zhu
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
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power consumption
high speed
multiscale
low power
neural network
scale space
ultra low power
low cost
compression algorithm
circuit design
delay insensitive
chip design
power management
vlsi circuits
cmos image sensor