Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking.
Jiri BarnatLubos BrimPavel SimecekM. WeberPublished in: TACAS (2008)
Keyphrases
- binary decision diagrams
- model checking
- temporal logic
- bounded model checking
- symbolic model checking
- linear temporal logic
- model checker
- automated verification
- partial order reduction
- temporal properties
- formal verification
- formal specification
- computation tree logic
- finite state
- finite state machines
- reachability analysis
- timed automata
- pspace complete
- linear time temporal logic
- transition systems
- formal methods
- epistemic logic
- process algebra
- verification method
- reactive systems
- concurrent systems
- asynchronous circuits
- modal logic